1. Field of Invention
The present invention relates to a method of manufacturing high-voltage metaloxide-semiconductor (MOS) devices. More particularly, the present invention relates to a method of manufacturing an assembly with different types of vertical high-voltage MOS devices.
2. Description of Related Art
As devices are miniaturized, channel length is also shortened, leading to higher operation speed. However, accompanying the shortening of the device channel is a problem referred to as short channel effect. In general, an electric field within a transistor channel is governed by the relationship Field=Voltage/Channel Length. Therefore, if the applied voltage to a transistor remains unchanged while its channel length is shortened, electrons will have higher energies because they are accelerating in a higher electric field. Consequently, the likelihood of an electrical breakdown is greatly increased.
Generally, a high-voltage MOS device is capable of functioning normally despite the application of a high voltage because an isolating layer and a drift region underneath the isolating layer serves to increase the distance of separation between the source/drain terminal and the gate terminal of the MOS device.
FIGS. 1A, 1B and 1C are cross-sectional views showing the structures of conventional high-voltage MOS devices.
In FIG. 1A, the high-voltage MOS device has a P.sup.- substrate 100, N.sup.- doped regions 101, N.sup.+ doped regions 102, and a gate layer 103. The N.sup.+ doped region 102 is the source/drain region, and the N.sup.- doped region 101 serves to increase the distance of separation between the source/drain terminal and the gate terminal.
In FIG. 1B, the high-voltage MOS device has a P.sup.- substrate 110. N.sup.- doped regions 111, N.sup.+ doped regions 112, spacers 113 and a gate layer 114. The N.sup.+ doped region 112 is the source/drain region, and the N.sup.- doped region 111 and the spacer 113 serve to increase the distance of separation between the source/drain terminal and the gate terminal.
In FIG. 1C, the high-voltage MOS device has a P.sup.- substrate 120, N.sup.- doped regions 121, N.sup.+ doped regions 122, field oxide (FOX) layer 123 and a gate layer 124. The N.sup.+ doped region 122 is the source/drain region, and the N.sup.- doped region 121 and the field oxide layer 123 serve to increase the distance of separation between the source/drain terminal and the gate terminal.
However, the high-voltage MOS devices shown in FIGS. 1A, 1B and 1C all have planar structures. These devices must be laterally laid out and hence sufficient space must be provided to accommodate the required isolation layer. With this type of design, the surface area needed to form these devices increases and the critical dimensions are difficult to reduce. Ultimately, the level of integration of these devices will be affected. In other words, it is difficult to shorten the channel length of these conventional high-voltage MOS devices, thus making the development of sub-micron high-voltage MOS devices impossible.
Furthermore, besides occupying a larger amount of surface area and therefore affecting the level of integration, it is difficult for conventional high-voltage devices to function normally when they are formed side-by-side with ordinary devices on the same integrated circuit. In other words, it is difficult to fabricate different types of high-voltage devices each having a definite range of operating voltage on the same integrated circuit.
In light of the foregoing, there is a need to provide an improved method of manufacturing high-voltage MOS devices.